Alignment Constraints¶

Cache Lines¶

One cache block is placed in one cache line. Fetching instructions from two cache lines in the same cycle is very hard. Normally, we can only fetch two instructions on the same cache line. So, if two instructions are on different cache lines, the superscalar processor will fetch a nop.

Execution Obeying Alignment Constraint¶

Addr     Instr
0x000    I0
0x004    J 0x204
0x200    -
0x204    I1
0x208    I2
0x20C    I3

       0    4    8    C
0x00X  | I0 | J  |    |    | 
0x20X  |    | I1 | I2 | I3 |
0x21X  |    |    |    |    |