I2OI¶
Pipeline Structure¶
Scoreboard¶
I2OI uses a scoreboard for avoiding hazards while issuing instructions inorder.
Reorder Buffer (ROB)¶
| State | S | ST | V | PReg |
|---|---|---|---|---|
| P | 1 | 0 | 0 | 0 |
| F | 0 | 1 | 1 | 1 |
- State - Pending or Free / Finished
- S - Speculative
- ST - Store bit
- V - whether the physical register file is valid
- PReg - the physical register file specifier
The Reorder Buffer is a queue with a head and a tail. The commit stage waits for the head to be finished.
Finished Store Buffer (FSB)¶
| V | Op | Addr | Data |
|---|---|---|---|
| 0 | ? | ? | ? |
- Only one entry is needed if one memory instruction is in flight at a time
- Single entry FSB makes allocation trivial.
- If we want to support more than one memory instruction, we need to worry about load / store address aliasing.
Pipeline Diagram¶
- r shows when a value is queued onto the reorder buffer
- C is when the new value is committed
- C and r can happen in the same cycle
Branch Resolution¶
- Squash on branch resolution - more complex, especially for ROB
- Squash on branch commit
- Squash as instructions commit - more resources used, simplest
Store Misses¶
Store misses add delays of ~3 cycles which is kinda bad. You can use retire stages to conduct them asynchronously while further instructions run (but you should be wary of any related hazards)