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I4

Pipeline Structure

Pasted image 20221021061041.png

There are three functional units here: * ALU - X * Memory - M * Multiplication - Y

Scoreboard

A scoreboard is used for issuing instructions. The architectural register files are where the information is read from / written to.

R P F 4 3 2 1 0
R1 1 X 0 0 1 0 0
R2 1 Y 0 1 0 0 0

P => Pending F => The functional unit the register is assigned to

The numbers indicate how far the register is from being available (i.e. the writeback stage)

Bits in the data availability shift right once after every cycle.

Pipeline Diagram

0 MUL R1, R2, R3    F  D  I  Y0 Y1 Y2 Y3 W 
1 ADDIU R11, R10, 1    F  D  I  X0 X1 X2 X3 W 
2 MUL R5, R1, R4          F  D  I  I  I  Y0 Y1 Y2 Y3 W 
3 MUL R7, R5, R6             F  D  D  D  I  I  I  I  Y0 Y1 Y2 Y3 W 
4 ADDIU R12,R11,1               F  F  F  D  D  D  D  I  X0 X1 X2 X3 W 
5 ADDIU R13,R12,1                        F  F  F  F  D  I  X0 X1 X2 X3 W 
6 ADDIU R14,R12,2                                    F  D  I  X0 X1 X2 X3 W
  • Stalling is done on the issue stage
  • Bypass is done from writeback for instructions in Y unit
  • Bypass is done from X0 for instructions in X unit