Data Hazard Resolution¶

Data Hazards in processors are majorly solved in one of two ways.

Stall¶

A Stall policy involves waiting for the desired resource to be fresh. The dependent instruction is 'Stalled' till this condition is satisfied.

1) add R1 R2 R3
2) add R2 R1 R3

Example¶

You can think of this as waiting till the TAs upload test cases to submit your code.

   1  2  3  4  5
1  F  D  X    
2     F  D

Instruction 2 wants the fresh value of R1, but knows that it won't be achieved till cycle 5. So it waits till cycle 5, looping in the decode phase, doing nothing.

   1  2  3  4  5
1  F  D  X  M  W
2     F  D  D  D

Depending upon the processor implementation, it may or may not be able to fetch the fresh value on the same cycle that it is written to. For my notes, I will assume that it cannot. Now that the fresh value of R1 has been stored, Instruction 2 can read it and continue processing

   1  2  3  4  5  6  7  8  9
1  F  D  X  M  W  
2     F  D  D  D  D  X  M  W

While Instruction 2 is stalling in the Decode phase, Instruction 3 would be stalling in the Fetch phase, and Instruction 4 will not execute at all.

   1  2  3  4  5  6  7
1  F  D  X  M  W  
2     F  D  D  D  D  X
3        F  F  F  F  D
4                    F

Instruction 3 is halted on Fetch just because Instruction 2 is already in decode. One stage of the processor can only handle one instruction at a time.

Bypass¶

A Bypass policy involves passing a value from one phase of the pipeline to the next. This can be complicated in practice, so we don't cover it in much detail.

Example¶

You can think of this as me passing you test-cases in advance before they're uploaded, which I would unfortunately never do.

   1  2  3  4  5
1  F  D  X  M  W
2     F  D  D  D

Consider this pipeline diagram, resulting from a stall policy. You may have noticed that we wait two cycles, even though the value of R1 was already confirmed at the end of Cycle 3.

In the bypass approach, we put a "bypass" line that will pass the value of R1 from X to D at the end of cycle 3. This way, the value can immediately be read on Cycle 4, eliminating the slow-down caused by stalling.

   1  2  3  4  5  6  7
1  F  D  X  M  W
          `-,[bypassed]
2     F  D  D  X  M  W

Scheduling¶

Scheduling involves requiring the user to arrange their code such as to avoid RAW errors. This involves the usage of nop instructions.

Speculation¶

Speculation involves looking ahead a few instructions, and running them out of order so as to avoid RAW hazards.