Structural And Control Hazards

Structural Hazard

Structural hazards occur when two instructions need the same hardware resource at the same time. One such example is trying to read from and write into a memory location simultaneously. This is typically not possible, but there are workarounds for it.

Control Hazard

Control hazards occur when you reach any branching instruction. The issue is that we don't immediately know which instruction to go to next.

[this is a part of a larger program]
...
1) bgt lbl R5 R6
2) add R1 R2 R3
3) add R1 R2 R3
4) add R1 R2 R3
5) add R1 R2 R3
6) lbl: add R3 R2 R1
...

   1  2
1  F  D

On cycle 2, you'd prefer to have another instruction entering the fetch phase, but you don't know which one.

Resolution of Control Hazards

Pipeline Stalling

Do nothing at all till the branch outcome is resolved. This is inefficient regardless of which outcome is achieved.

Speculate

Your machine makes an educated guess on whether or not this code would lead to branching. For the sake of simplicity, we assume that the educated guess is always No Branch. Then, it speculatively starts executing the next instruction. Suppose branches are resolved at Decode in this ISA / machine.

   1  2  3 | 4  5  6  7  8 
1  F  D  X | M  W
2     F  D | X  M  W
3        F | D  X  M  W
6          | F  D  X  M  W

After cycle 3, we decide to perform branching and set PC to 6. This guess has been incorrect. However, leaving this execution as is will lead to the unintended modification of R1 caused by running instructions 2 and 3, which were never supposed to be executed.

To resolve this, we stuff instruction 2 and 3 with nops.

   1  2  3 | 4  5  6  7  8 
1  F  D  X | M  W
2     F  D | -  -  -
3        F | -  -  -  -
6          | F  D  X  M  W