Iron Law Of Processor Performance¶
Iron Law of Processor Performance¶
$$ \frac{Time}{Program} = \frac{Instructions}{Program} \times \frac{Cycles}{Instruction} \times \frac{Time}{Cycle} $$ The speed of two processors is compared with the Iron Law.
Parameters of the Iron Law¶
- Time / Cycle - The time taken for the processor to finish one processing cycle. This depends completely on the hardware.
- Cycles / Instruction - The number of cycles taken on average to execute an instruction. Note that while not mentioned here, the CPI is also measured relative to the benchmark program. The CPI can vary from program-to-program (A program with a lot of stalling will end up with higher CPI than a program with no stalling).
- Instruction / Program - The number of instructions present in the benchmark that we are comparing the processors on.
- Instructions / Second - This is just a combination of two factors. We measure performance often in MIPS (Millions of Instructions per Second).
Benchmark¶
Benchmarks are programs that simulate the use case of the processor. They're supposed to evaluate how quickly it'll be able to perform in practice. They all contain code that performs a certain task in a certain way. An example might be calculating the factorial of a number recursively. The code will vary between ISAs, but the purpose will be the same. Of course, benchmarks are far more complex than this in practice.
What affects which parameter?¶
RISC vs CISC¶
RISC Processors have lower CPI than CISC as they use simpler instructions, but end up with higher Instructions in the benchmark. This makes an objective comparison in the speed of RISC and CISC ISAs impossible {which is what you lost marks over in Quiz 2 ;-) }
Pipelining¶
A non-pipelined processor executes one instruction in one clock cycle, which combines all the five phases. This clock cycle is longer than one individual phase, but typically a bit shorter than all the phases combined. Meanwhile a pipelined processor has lower Time / Cycle with higher CPI. While an objective comparison between the two isn't possible, a good pipelined processor will typically perform faster.
Processor¶
A faster processor means lower Time / Cycle. This makes the processor work faster (shocking). A 5GHz processor will be always faster than a 2GHz processor running the same ISA.
Branch Delay Penalty¶
Code that involves a lot of branching can lead to a lot of killed instructions. This causes what is referred to as a Branch Delay Penalty. One can avoid this by using less branching, or (preferably) a sophisticated branch predictor.