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Pipelining

In a pipelined processor, different steps of instruction processing are assigned to different "phases". Each of these "phases" are isolated, which allows for having multiple instructions in different phases at the same time.

Why Pipeline

Pipelined processors are significantly faster than non-pipelined ones, if you can handle the complications they bring along with them properly.

Phases of the Classic RISC Pipeline

  • Fetch (F) - In this phase, the instruction is loaded in from the memory.
  • Decode (D) - The instruction's individual parts are decoded in this phase, such as the opcode, the sources, and destinations. The source values are loaded from memory / registers during this phase as well.
  • Execute (E/X) - These source values are sent to the ALU for processing, if needed.
  • Memory (M) - Values that need to be written into the memory are written here.
  • Writeback (W) - Values that need to be written into registers are written here.

Pipeline Diagram

In a pipeline diagram, we note down the state of the machine on each cycle. Each cycle is a column, and each row represents an instruction

add R1 R2 R3
add R1 R2 R3
add R1 R2 R3
add R1 R2 R3
add R1 R2 R3

has the pipeline diagram

   1  2  3  4  5  6  7  8  9
1  F  D  X  M  W
2     F  D  X  M  W
3        F  D  X  M  W
4           F  D  X  M  W
4              F  D  X  M  W

Note that on one cycle, one phase of the pipeline may only contain one instruction in it. in an \(n\) phase pipelined processor, the maximum number of instructions that can be executed simultaneously in that processor is \(n\)